MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 411

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
Table 17-2 lists signals in alphabetical order by abbreviated name.
Timer outputs
Parallel port
Serial clock line
Serial data line
Motorola test mode
Motorola test mode
High impedance
Processor clock out
Processor status/debug
data
Test clock
Test reset/
Development serial
clock
Test mode select/
Breakpoint
Test data input/
Development serial
input
Test data output/
Development serial
output
If there is no arbiter, BG should be tied low; otherwise, it should be negated.
These data pins are sampled at reset for configuration.
AA_CONFIG
ADDR_CONFIG
AS
Abbreviation
Signal Name
Auto-acknowledge configuration
Address configuration
Address strobe
Table 17-2. MCF5407 Alphabetical Signal Index
Table 17-1. MCF5407 Signal Index (Continued)
TOUT[1:0]
PP[15:0]
SCL
SDA
MTMOD0
MTMOD[3:1]
HIZ
PSTCLK
PSTDDATA[7:0]
TCK
TRST/DSCLK
TMS/BKPT
TDI/DSI
TDO/DSO
Abbreviation
Section 17.14, “Debug Module/JTAG Signals”
Section 17.11, “Parallel I/O Port (PP[15:0])”
Section 17.13, “Debug and Test Signals”
Section 17.12, “I
Chapter 17. Signal Descriptions
Signal Name
Outputs waveform or pulse.
Interfaces with I/O; multiplexed with
bus address and attribute signals.
Clock signal for I
Serial data port for I
Puts processor in functional or
emulator mode
Reserved
Assertion three-states all outputs
Output clock used for PSTDDATA
Displays captured processor data
and breakpoint status
Clock signal for IEEE 1149.1 JTAG
Asynchronous reset for JTAG;
debug module clock input
TMS (JTAG)/hardware breakpoint
(debug)
Multiplexed serial input for the JTAG
or background debug module
Multiplexed serial output for the
JTAG or background debug module
2
C Module Signals”
Function
2
C operation
2
C operation
Clock/reset
Clock/reset
Bus
Function
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
Driven
Driven
Reset
Open
Open
Input
drain
drain
High
—
—
—
—
—
—
—
—
User cfg 17-20
I/O
I/O
Pull-Up Page
Down
I
I
Low
Up
Up
Up
Up
Up
Up
Overview
17-14
17-15
Page
17-9
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17-19
17-19
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17-20
17-20
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