MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 379

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

detection, if 8-bit characters are not required, is to use software to calculate parity and
append it to the 5-, 6-, or 7-bit character.
14.5.5 Bus Operation
This section describes bus operation during read, write, and interrupt acknowledge cycles
to the UART module.
14.5.5.1 Read Cycles
The UART module responds to reads with byte data. Reserved registers return zeros.
14.5.5.2 Write Cycles
The UART module accepts write data as bytes. Write cycles to read-only or reserved
registers complete normally without exception processing, but data is ignored.
14.5.5.3 Interrupt Acknowledge Cycles
The UART module supplies the interrupt vector in response to a UART IACK cycle. If
UIVRn is not initialized to provide a vector number, a spurious exception is taken if an
interrupt is generated. This works in conjunction with the interrupt controller, which allows
a programmable priority level.
14.5.6 Programming
The software flowchart, Figure 14-39, consists of the following:
• UART module initialization—These routines consist of SINIT and CHCHK (sheets
• I/O driver routine—This routine (sheets 4 and 5) consists of INCH, the terminal
1 and 2). Before SINIT is called at system initialization, the calling routine allocates
2 words on the system stack. On return to the calling routine, SINIT passes UART
status data on the stack. If SINIT finds no errors, the transmitter and receiver are
enabled. SINIT calls CHCHK to perform the checks. When called, SINIT places the
UART in local loop-back mode and checks for the following errors:
— Transmitter never ready
— Receiver never ready
— Parity error
— Incorrect character received
input character routine which gets a character from the receiver, and OUTCH, which
sends a character to the transmitter.
The UART module is accessed by the CPU with zero wait
states, as CLKIN is used for the UART module.
Chapter 14. UART Modules
NOTE:
Operation
14-37