MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 7

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.6.2
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.8
2.8.1
2.8.2
2.9
3.1
3.1.0.1
3.1.0.2
3.1.0.3
3.1.0.4
3.2
4.1
4.2
4.3
4.4
4.4.1
4.5
4.5.1
4.6
4.7
4.8
4.8.1
4.8.2
4.9
4.9.1
4.9.1.1
4.9.1.2
4.9.1.3
Paragraph
Number
Execution Timings ............................................................................................ 2-23
Exception Processing Overview ....................................................................... 2-31
ColdFire Instruction Set Architecture Enhancements....................................... 2-36
Overview............................................................................................................. 3-1
MAC Instruction Execution Timings.................................................................. 3-5
Interactions between Local Memory Modules ................................................... 4-1
SRAM Overview ................................................................................................ 4-1
SRAM Operation ................................................................................................ 4-2
SRAM Programming Model............................................................................... 4-3
SRAM Initialization............................................................................................ 4-4
Power Management ............................................................................................ 4-6
Cache Overview.................................................................................................. 4-6
Cache Organization............................................................................................. 4-8
Cache Operation................................................................................................ 4-11
Instruction Set Summary .............................................................................. 2-19
MOVE Instruction Execution Timing .......................................................... 2-25
Execution Timings—One-Operand Instructions .......................................... 2-26
Execution Timings—Two-Operand Instructions.......................................... 2-27
Miscellaneous Instruction Execution Times................................................. 2-29
Branch Instruction Execution Times ............................................................ 2-30
Exception Stack Frame Definition................................................................ 2-32
Processor Exceptions .................................................................................... 2-34
SRAM Base Address Registers (RAMBAR0/RAMBAR1)........................... 4-3
SRAM Initialization Code .............................................................................. 4-5
Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified............. 4-8
The Cache at Start-Up..................................................................................... 4-9
Caching Modes ............................................................................................. 4-13
MAC Programming Model......................................................................... 3-2
General Operation....................................................................................... 3-3
MAC Instruction Set Summary .................................................................. 3-4
Data Representation.................................................................................... 3-4
Cacheable Accesses .................................................................................. 4-14
Write-Through Mode (Data Cache Only)................................................. 4-14
Copyback Mode (Data Cache Only)......................................................... 4-14
Hardware Multiply/Accumulate (MAC) Unit
CONTENTS
Local Memory
Chapter 3
Chapter 4
Contents
Title
Number
Page
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