MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 252

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Interrupt Controller Registers
The SIM provides the following registers for managing interrupts:
9.2 Interrupt Controller Registers
The interrupt controller register portion of the SIM memory map is shown in Table 9-2.
Each internal interrupt source has its own interrupt control register (ICR0–ICR9), shown in
Table 9-2 and described in Section 9.2.1, “Interrupt Control Registers (ICR0–ICR9).”
9-2
MBAR
Offset
0x04C
0x040
0x044
0x048
0x050
0x054
• Each potential interrupt source is assigned one of the 10 interrupt control registers
• The interrupt mask register (IMR) provides bits for masking individual interrupt
• The interrupt pending register (IPR) provides bits for indicating when an interrupt
• The autovector register (AVEC) controls whether the SIM supplies an autovector or
• The interrupt port assignment register (IRQPAR) provides the level assignment of
(ICR0–ICR9), which are used to prioritize the interrupt sources.
sources.
request is being made (regardless of whether it is masked in the IMR).
executes an external interrupt acknowledge cycle for each IRQ.
the primary external interrupt pins—IRQ5, IRQ3, and IRQ1.
UART0 (ICR4) [p. 9-3]
DMA2 (ICR8) [p. 9-3]
timer (ICR0) [p. 9-3]
Software watchdog
[31:24]
Table 9-1. Interrupt Controller Registers
Table 9-2. Interrupt Control Registers
MBAR Offset
0x04C
0x04D
0x04E
0x04F
0x050
0x051
0x052
Interrupt Control Registers (ICRs) [p. 9-3]
UART1 (ICR5) [p. 9-3]
Timer0 (ICR1) [p. 9-3]
DMA3 (ICR9) [p. 9-3]
MCF5407 User’s Manual
Interrupt pending register (IPR) [p. 9-6]
Interrupt mask register (IMR) [p. 9-6]
Reserved
[23:16]
Register
ICR0
ICR1
ICR2
ICR3
ICR4
ICR5
ICR6
Software watchdog timer
Timer0
Timer1
I
UART0
UART1
DMA0
2
C
Timer1 (ICR2) [p. 9-3]
DMA0 (ICR6) [p. 9-3]
Name
[15:8]
Reserved
DMA1 (ICR7) [p. 9-3]
Autovector register
I
2
C (ICR3) [p. 9-3]
(AVR) [p. 9-5]
[7:0]