MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 432

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Data Transfer Operation
The timing relationships between CLKIN and chip select (CS[7:0]), byte enable/byte write
enables (BE/BWE[3:0]), and output enable (OE) are similar to their relationships with
address strobe (AS) in that all transitions occur during the low phase of CLKIN. However,
as shown in Figure 18-3, differences in on-chip signal routing and external loading may
prevent signals from asserting simultaneously.
18.4.1 Bus Cycle Execution
When a bus cycle is initiated, the MCF5407 first compares its address with the base address
and mask configurations programmed for chip selects 0–7 (CSCR0–CSCR7) and for
DRAM blocks 0 and 1 address and control registers (DACR0 and DACR1). If the driven
address matches a programmed chip select or DRAM block, the appropriate chip select is
asserted or the DRAM block is selected using the specifications programmed in the
respective configuration register. Otherwise, the following occurs:
18-4
• If the address and attributes do not match in CSCR or DACR, the MCF5407 runs an
• If an address and attribute match in multiple CSCRs, the matching chip-select
• If an address and attribute match both DACRs or a DACR and a CSCR, the operation
external burst-inhibited bus cycle with a default of external termination on a 32-bit
port.
signals are driven; however, the MCF5407 runs an external burst-inhibited bus cycle
with external termination on a 32-bit port.
is undefined.
BE/BWE[3:0]
Figure 18-2. Connections for External Memory Port Sizes
Figure 18-3. Chip-Select Module Output Timing Diagram
CS[7:0]
AS, OE
CLKIN
Byte Enable
32-Bit Port
16-Bit Port
Processor
8-Bit Port
Data Bus
External
Memory
Memory
Memory
MCF5407 User’s Manual
D[31:24]
Byte 0
Byte 0
Byte 2
Byte 0
Byte 1
Byte 2
Byte 3
BE0
D[23:16]
Byte 1
Byte 1
Byte 3
BE1
indeterminate values
Driven with
indeterminate values
D[15:8]
Byte 2
BE2
Driven with
Byte 3
D[7:0]
BE3