MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 426

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I2C Module Signals
Motorola recommends that D4 be driven during reset to a logic level.
17.12 I
The I
peripherals with an I
converter). Devices connected to the I
17.12.1 I
The bidirectional, open-drain I
module operation. The I
I
17.12.2 I
The bidirectional, open-drain I
serial I
17.13 Debug and Test Signals
The signals in this section interface with external I/O to provide processor status signals.
17.13.1 Test Mode (MTMOD[3:0])
The test mode signals choose between multiplexed debug module and JTAG signals. If
MTMOD0 is low, the part is in normal and background debug mode (BDM); if it is high,
it is in normal and JTAG mode. All other MTMOD values are reserved; MTMOD[3:1]
should be tied to ground and MTMOD[3:0] should not be changed while RSTI is negated.
17.13.2 High Impedance (HIZ)
The assertion of HIZ forces all output drivers to high-impedance state. The timing on HIZ
is independent of the clock. Note that HIZ does not override the JTAG operation;
TDO/DSO can be forced to high impedance by asserting TRST.
17.13.3 Processor Clock Output (PSTCLK)
The internal PLL generates this output signal, and is the processor clock output that is used
as the timing reference for the debug bus timing (PSTDDATA[7:0]). PSTCLK is at the
same frequency as the core processor and cache memory.
17-20
2
C devices drive this signal to synchronize I
2
C module acts as a two-wire, bidirectional serial interface between the MCF5407 and
2
C interface.
2
2
2
C Module Signals
C Serial Clock (SCL)
C Serial Data (SDA)
2
C interface (such as LED controller, A-to-D converter, or D-to-A
2
C module controls this signal when the bus is in master mode; all
2
2
C serial data signal (SDA) is the data input/output for the
C serial clock signal (SCL) is the clock signal for I
MCF5407 User’s Manual
2
C must have open-drain or open-collector outputs.
2
C timing.
2
C