MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 537
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MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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A
Addressing mode summary, 2-15
Arbitration
Architecture
B
Branch acceleration, 2-4
Branch instruction execution
Bus arbitration control, 6-11
Bus master park register, 6-11
Bus operation
between masters, 6-14
bus control, 6-11
for internal transfers, 6-12
Harvard memory, 2-6
instruction set
timing, 2-30
bus errors, 18-17
characteristics, 18-2
control signals, 18-1
data transfer
external master transfers
features, 18-1
interrupt exceptions, 18-17
misaligned operands, 18-16
reset operation
additions, 2-18
enhancements, 2-36
back-to-back cycles, 18-10
burst cycles
cycle execution, 18-4
cycle states, 18-5
fast-termination cycles, 18-9
operation, 18-2
read cycle, 18-7
write cycle, 18-8
general, 18-21
two-device arbitration protocol, 18-25
two-wire mode, 18-25
master, 18-34
overview, 18-33
software watchdog, 18-35
line read bus, 18-12
line transfers, 18-12
line write bus, 18-14
mixed port sizes, 18-15
overview, 18-11
INDEX
Index
C
Cache
Chip-select module
Clock
ColdFire core
Condition code register, 2-9
CPU STOP instruction, 6-10
D
Data registers, A-13
Debug
DMA controller module
DRAM controller
configuration register, 2-12
registers, access control, 2-12
8-, 16-, and 32-bit port sizing, 10-4
enable signals, 17-15
operation, 10-2
overview, 10-1
registers, 10-5, 10-6, B-2
signals, 10-1
PLL control, 6-10
exception stack frame definition, A-11
features and enhancements, 2-1
module enhancements, 2-6
system interface, 1-12
byte count registers, 12-7
programming model, 12-5
signal description, 12-2
source address registers, 12-7
transfer overview, 12-4
asynchronous mode signals, 11-4
asynchronous operation
general guidelines, 11-8
non-page mode, 11-11
refresh operation, 11-16
registers, 11-3
general, 10-3
global, 10-4
code example, 10-9
control, 10-8
mask, 10-7
burst page mode, 11-12
continuous page mode, 11-13
extended data out, 11-15
general, 11-4
register set, 11-4
Index-1
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