MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 378

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Operation
Functional timing information for multidrop mode is shown in Figure 14-38.
A character sent from the master station consists of a start bit, a programmed number of
data bits, an address/data (A/D) bit flag, and a programmed number of stop bits. A/D = 1
indicates an address character; A/D = 0 indicates a data character. The polarity of A/D is
selected through UMR1n[PT]. UMR1n should be programmed before enabling the
transmitter and loading the corresponding data bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream, regardless
of whether it is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and
loads the character into the receiver holding register FIFO stack provided the received A/D
bit is a one (address tag). The character is discarded if the received A/D bit is zero (data
tag). If the receiver is enabled, all received characters are transferred to the CPU through
the receiver holding register stack during read operations.
In either case, the data bits are loaded into the data portion of the stack while the A/D bit is
loaded into the status portion of the stack normally used for a parity error (USRn[PE]).
Framing error, overrun error, and break detection operate normally. The A/D bit takes the
place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this
mode may still contain error detection and correction information. One way to provide error
14-36
USRn[RxRDY]
USRn[TxRDY]
Transmitter
Receiver
Enabled
Enabled
internal
module
internal
module
select
select
RxD
TxD
UMR1n[PM] = 11
UMR1n[PT] = 1
UMR1n
UMR1n[PM] = 11
Figure 14-38. Multidrop Mode Timing Diagram
[PM] = 11
A/D
ADD 1
0
UMR1n[PT] = 0
ADD1
ADD1
A/D
A/D
C0
MCF5407 User’s Manual
1
1
ADD 1
Peripheral Station
C0
C0
Master Station
A/D
A/D
Status Data
UMR1n[PT] = 2
(C0)
ADD 2
ADD2
ADD2
A/D
A/D
1
1
Status Data
(ADD 2)
A/D
0