MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 43
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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sign-extended
If <condition>
<operations>
<operations>
Instruction
Address
MSW
LSW
MSB
←→
then
LSB
msb
else
lsb
<<
>>
Bit
→
d
C
N
~
&
{}
()
V
X
Z
^
/
|
n
Arithmetic division
Invert; operand is logically complemented
Logical AND
Logical OR
Logical exclusive OR
Shift left (example: D0 << 3 is shift D0 left 3 bits)
Shift right (example: D0 >> 3 is shift D0 right 3 bits)
Source operand is moved to destination operand
Two operands are exchanged
All bits of the upper portion are made equal to the high-order bit of the lower portion
Test the condition. If true, the operations after ‘then’ are performed. If the condition is false and the
optional ‘else’ clause is present, the operations after ‘else’ are performed. If the condition is false
and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description
as an example.
Optional operation
Identifies an indirect address
Displacement value, n-bits wide (example: d
Calculated effective address (pointer)
Bit selection (example: Bit 3 of D0)
Least significant bit (example: lsb of D0)
Least significant byte
Least significant word
Most significant bit
Most significant byte
Most significant word
Carry
Negative
Overflow
Extend
Zero
Table ii Notational Conventions (Continued)
Condition Code Register Bit Names
Subfields and Qualifiers
About This Book
Operand Syntax
16
is a 16-bit displacement)
Terminology and Notational Conventions
xliii
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