MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 109

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

INTOUCH
Operation:
Assembler Syntax INTOUCH <Ay>
Attributes:
Description: Generates an instruction fetch reference at address (Ay). If the referenced
address space is a cacheable region, this instruction can be used to prefetch a 16-byte packet
into the processor’s instruction cache. If the referenced instruction address is a
non-cacheable space, the instruction effectively performs no operation.
The INTOUCH instruction can be used to prefetch, and with the later setting of CACR[11],
lock specific memory lines in the processor’s instruction cache. This function may be
desirable in systems where deterministic real-time performance is critical.
Condition Codes:
Instruction Fields:
Instruction
Format:
• Register field—Specifies the destination address register number.
15
1
Operand sizes supported
14
1
Opcode present
If Supervisor State
else TRAP
Unsized
Not affected.
INTOUCH
13
1
12
1
then Instruction Fetch Touch @ <Ay>
Chapter 2. ColdFire Core
11
0
Instruction Fetch Touch
10
1
ColdFire Instruction Set Architecture Enhancements
0
9
V2, V3 Core
0
8
No
—
0
7
0
6
5
1
4
0
V4 Core
INTOUCH
Yes
—
1
3
2
REGISTER
1
2-43
0