MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 511
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MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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Quantity:
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multiplexed with D[7:3]. See for D[2:0]/DIVIDE[2:0] encodings sampled at reset. Note
that Table A-7 and Table A-8 configure the global, or boot, CS0 that is used to access boot
ROM out of reset. CS0 is the only chip select active out of reset until other chip selects
become valid. Both the wait states and port size of boot memory accessed by boot CS0 are
programmed through these bits.
Table A-8 shows configurations for D[6:5]/PS[1:0].
Table A-9 initializes the pin assignment register of the parallel I/O port to be either parallel
I/O or to be the upper address bus bits along with various attribute and control signals at
reset to give the user the option to access a broader addressing range of memory, if desired.
Table A-10 shows configurations for D3/BE_CONFIG. Because some boot memories
require byte enables to be active only during writes, the functionality of byte enables,
BE[3:0], can be programmed at reset.
D[2:0]/DIVIDE[2:0] configurations are shown in Table A-5.
After RSTI is negated, 32 bits of CPU configuration information are loaded into data
register D0 and 32 bits of internal memory information are loaded in D1. Because these
registers are completely uninitialized on previous ColdFire devices, this feature allows
users to identify the MCF5407 through software. Values D1 = 0x0630_0530 and D0 =
Table A-10. D3/BE_CONFIG, BE[3:0] Boot Configuration
Table A-9. D4/ADDR_CONFIG, Address Pin Assignment
Table A-7. D7/AA, Automatic Acknowledge of Boot CS0
D4/ADDR_CONFIG
D3/BE_CONFIG
Table A-8. D[6:5]/PS[1:0], Port Size of Boot CS0
Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407
0
1
0
1
D[6:5]/PS[1:0]
D7/AA
0
1
00
01
1x
BE[3:0] are enabled as byte write enables only
BE[3:0] are enabled as byte enables for reads and writes
PP[15:0], defaulted to inputs upon reset
ADDR[31:24]/TIP/DREQ[1:0]/TM[2:1]
Configuration Pin Assignment Register at Reset
Disabled
Enabled with 15 wait states
Configuration of Byte Enables for Boot CS0
Boot CS0 AA Configuration at Reset
Boot CS0 Port Size at Reset
32-bit port
16-bit port
8-bit port
Reset Initialization Modifications
A-9
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