MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 238

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Interface Features
Figure 8-1 is a block diagram of the I
Figure 8-1 shows the relationships of the I
8-2
• Start and stop signal generation/detection
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus-busy detection
• I
• I
• I
• I
• I
Divider Register
I
2
Registers and ColdFire Interface
C Frequency
2
2
2
2
2
C address register (IADR)
C frequency divider register (IFDR)
C control register (I2CR)
C status register (I2SR)
C data I/O register (I2DR)
(IFDR)
Control
Clock
Input
Sync
I
2
Figure 8-1. I
Register
C Control
(I2CR)
SCL
Start, Stop,
Arbitration
Control
and
MCF5407 User’s Manual
SDA
2
2
C module.
C Module Block Diagram
IRQ
I
2
Register
C Status
(I2SR)
2
C registers, listed below:
Compare
Register
Address
In/Out
Shift
Data
Address Decode
Internal Bus
Address
I/O Register
I
2
(I2DR)
C Data
I
2
C Address
Data MUX
Register
(IADR)
Data