MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 415

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

if a longword access occurs at a misaligned offset of 0x1, a byte is transferred first (SIZ[1:0]
= 01), a word is next transferred at offset 0x2 (SIZ[1:0] = 10), then the final byte is
transferred at offset 0x4 (SIZ[1:0] = 01).
For aligned transfers larger than the port size, SIZ[1:0] behaves as follows:
For burst-inhibited transfers, SIZ[1:0] changes with each TS assertion to reflect the next
transfer size. For transfers to port sizes smaller than the transfer size, SIZ[1:0] indicates the
size of the entire transfer on the first access and the size of the current port transfer on
subsequent transfers. For example, for a longword write to an 8-bit port, SIZ[1:0] = 00 for
the first byte transfer and 01 for the next three.
17.2.5 Transfer Start (TS)
The MCF5407 asserts TS during the first clock cycle when address and attributes (TM, TT,
TIP, R/W, and SIZ) are valid. TS is negated in the following clock cycle. When the
MCF5407 is not the bus master, TS is an input.
17.2.6 Address Strobe (AS)
Address strobe (AS) is asserted to indicate when the address is stable at the start of a bus
cycle. The address and attributes are guaranteed to be valid during the entire period that AS
is asserted. This signal is asserted and negated on the falling edge of the clock. When the
MCF5407 is not the bus master, AS is an input.
17.2.7 Transfer Acknowledge (TA)
When the MCF5407 is bus master, the external system drives this input to terminate the bus
transfer. The bus continues to be driven until this synchronous signal is asserted. For write
cycles, the processor continues to drive data one clock after TA is asserted. During read
cycles, the peripheral must continue to drive data until TA is recognized.
If all bus cycles support fast termination, TA can be tied low. However, note that TA cannot
be tied low if potential external bus masters are present. The MCF5407 drives TA for an
• If bursting is used, SIZ[1:0] stays at the size of transfer.
• If bursting is inhibited, SIZ[1:0] first shows the size of the transfer and then shows
the port size.
Table 17-4. Bus Cycle Size Encoding
Chapter 17. Signal Descriptions
SIZ[1:0]
00
01
10
11
Longword
Byte
Word
Line
Port Size
MCF5407 Bus Signals
17-9