DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 122

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
5.3.6
The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests.
• ISR16
• ISR
Note:
Rev. 3.00, 03/04, page 80 of 830
Bit
7 to 0 IRQ15F to
Bit
7 to 0 IRQ7F to
*
Bit Name
IRQ8F
Bit Name
IRQ0F
IRQ Status Registers (ISR16, ISR)
ExIRQn stands for ExIRQ7 to ExIRQ2.
Initial Value
All 0
Initial Value
All 0
R/W
R/W
R/W
R/W
Description
[Setting condition]
[Clearing conditions]
Description
[Setting condition]
[Clearing conditions]
When the interrupt source selected by the
ISCR16 registers occurs
When reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
When interrupt exception handling is
executed when low-level detection is set
and IRQn or ExIRQn input is high
When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set
(n = 15 to 8)
When the interrupt source selected by the
ISCR registers occurs
When reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
When interrupt exception handling is
executed when low-level detection is set
and IRQn or ExIRQn* input is high
When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set
(n = 7 to 0)

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