DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 513
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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15.4.4
In I
and returns an acknowledge signal. The slave device transmits data.
The master device transmits data containing the slave address and R/W (1: read) in the first frame
following the start condition issuance in master transmit mode, selects the slave device, and then
switches the mode for receive operation.
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 15.10 shows the sample flowchart for the operations in master receive mode (HNDS = 1).
2
C bus format master receive mode, the master device outputs the receive clock, receives data,
Figure 15.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)
Master Receive Operation
No
No
Set HNDS = 1 in ICXR
Set ACKB = 0 in ICSR
Set ACKB = 1 in ICSR
Set TRS = 0 in ICCR
Master receive mode
Set TRS = 1 in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Set BBSY = 0 and
SCP = 0 in ICCR
Last receive?
Read ICDR
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
End
Yes
Yes
No
Yes
[1] Select receive mode.
[2] Start receiving. The first read is a dummy read.
[5] Read the receive data (for the second and subsequent read)
[3] Wait for 1 byte to be received.
[4] Clear IRIC.
[6] Set acknowledge data for the last reception.
[7] Read the receive data.
[8] Wait for 1 byte to be received.
[9] Clear IRIC.
[10] Read the receive data.
[11] Set stop condition issuance.
(Set IRIC at the rise of the 9th clock for the receive frame)
Dummy read to start receiving if the first frame is
the last receive data.
Generate stop condition.
Rev. 3.00, 03/04, page 471 of 830
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