DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 493
![MCU 16BIT FLASH 3V 512K 144-TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously
without CPU intervention. The DTC does not support IIC_4 and IIC_5.
2
When, with the I
C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag (the
DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission
2
start condition or stop condition after a slave address (SVA) or general call address match in I
C
bus format slave mode.
Even when the IRIC flag and IRTR flag are set, the ICDRE or ICDRF flag may not be set. The
IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous
transfer using the DTC. The ICDRE or ICDRF flag is cleared, however, since the specified
number of ICDR reads or writes have been completed.
Tables 15.4 and 15.5 show the relationship between the flags and the transfer states.
Rev. 3.00, 03/04, page 451 of 830
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