DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 576
![MCU 16BIT FLASH 3V 512K 144-TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Note:
• STR3
Rev. 3.00, 03/04, page 534 of 830
Bit
0
Bit
7
6
5
4
3
2
(When TWRE = 0 and SELSTR3 = 1)
Bit Name Initial Value Slave Host Description
OBF3A
Bit Name Initial Value Slave Host Description
DBU37
DBU36
DBU35
DBU34
C/D3
DBU32
*
Only 0 can be written to clear the flag.
0
All 0
0
0
R/(W)* R
R/W
R
R/W
R/W
R/W
R
R
R
Defined by User
The user can use these bits as necessary.
Command/Data
When the host processor writes to an IDR3 register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR3 contains data or a command.
0: Content of input data register (IDR3) is data
1: Content of input data register (IDR3) is a command
Defined by User
The user can use this bit as necessary.
Output Data Register Full
Indicates whether or not there is transmit data in
ODR3.
0: There is not transmit data in ODR3
[Clearing condition]
When the host processor reads ODR3 using I/O
read cycle, or the slave processor writes 0 to the
OBF3A bit
1: There is transmit data in ODR3
[Setting condition]
When the slave processor writes to ODR3
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