DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 35

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 25.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)....................... 790
Figure 25.7 External Clock Input Timing................................................................................... 790
Figure 25.8 Timing of External Clock Output Stabilization Delay Time ................................... 791
Figure 25.9 Subclock Input Timing ............................................................................................ 791
Figure 25.10 Reset Input Timing................................................................................................ 792
Figure 25.11 Interrupt Input Timing........................................................................................... 793
Figure 25.12 Basic Bus Timing/2-State Access.......................................................................... 795
Figure 25.13 Basic Bus Timing/3-State Access.......................................................................... 796
Figure 25.14 Basic Bus Timing/3-State Access with One Wait State ........................................ 797
Figure 25.15 Burst ROM Access Timing/2-State Access........................................................... 798
Figure 25.16 Burst ROM Access Timing/1-State Access........................................................... 799
Figure 25.17 Multiplex Bus Timing/Data 2-State Access .......................................................... 801
Figure 25.18 Multiplex Bus Timing/Data 3-State Access .......................................................... 801
Figure 25.19 I/O Port Input/Output Timing................................................................................ 804
Figure 25.20 FRT Input/Output Timing ..................................................................................... 804
Figure 25.21 FRT Clock Input Timing ....................................................................................... 804
Figure 25.22 8-Bit Timer Output Timing ................................................................................... 804
Figure 25.23 8-Bit Timer Clock Input Timing ........................................................................... 805
Figure 25.24 8-Bit Timer Reset Input Timing ............................................................................ 805
Figure 25.25 PWM, PWMX Output Timing .............................................................................. 805
Figure 25.26 SCK Clock Input Timing....................................................................................... 805
Figure 25.27 SCI Input/Output Timing (Clock Synchronous Mode) ......................................... 806
Figure 25.28 A/D Converter External Trigger Input Timing...................................................... 806
Figure 25.29 WDT Output Timing (RESO) ............................................................................... 806
2
Figure 25.30 I
C Bus Interface Input/Output Timing ................................................................. 808
Figure 25.31 LPC Interface (LPC) Timing................................................................................. 809
Figure 25.32 JTAG ETCK Timing ............................................................................................. 810
Figure 25.33 Reset Hold Timing ................................................................................................ 810
Figure 25.34 JTAG Input/Output Timing................................................................................... 810
Figure 25.35 Connection of VCL Capacitor............................................................................... 816
Appendix
Figure C.1 Package Dimensions (TFP-144) ............................................................................... 820
Rev. 3.00, 03/04, page xxxiii of xl