DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 644

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
18.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 indicates
the A/D conversion time.
As indicated in figure 18.2, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in table 18.3.
In scan mode, the values given in table 18.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 266 states (fixed) when CKS = 0 and 134 states
(fixed) when CKS = 1.
Use the conversion time of 134 state only when the system clock (φ) is 16 MHz or lower.
Rev. 3.00, 03/04, page 602 of 830
SPL
). The length of t
Input Sampling and A/D Conversion Time
Address
Write signal
Input sampling
timing
ADF
φ
[Legend]
(1):
(2):
t
t
t
D
SPL
CONV
:
: Input sampling time
: A/D conversion time
D
ADCSR write cycle
ADCSR address
A/D conversion start delay
varies depending on the timing of the write access to ADCSR. The total
(1)
(2)
t
Figure 18.2 A/D Conversion Timing
D
t
SPL
D
) passes after the ADST bit in ADCSR is set to
t
CONV
CONV
) includes t
D
and the input sampling time

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