DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 488
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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15.3.6
ICCR controls the I
Rev. 3.00, 03/04, page 446 of 830
Bit
7
6
5
4
Bit Name
ICE
IEIC
MST
TRS
I
2
C Bus Control Register (ICCR)
2
Initial
Value
0
0
0
0
C bus interface and performs interrupt flag confirmation.
R/W
R/W
R/W
R/W
R/W
Description
I
0: I
1: I
I
0: Disables interrupts from the I
1: Enables interrupts from the I
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they lose
in a bus contention in master mode of the I
In slave receive mode with I
the first frame immediately after the start condition
automatically sets these bits in receive mode or transmit
mode by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.
2
2
C Bus Interface Enable
C Bus Interface Interrupt Enable
interface module internal state is initialized. SAR and
SARX can be accessed.
reception, they are connected to the SCL and SDA pins,
and the I
accessed.
2
2
C bus interface modules are stopped and I
C bus interface modules can perform transfer and
2
C bus can be driven. ICMR and ICDR can be
2
C bus format, the R/W bit in
2
2
C bus interface to the CPU.
C bus interface to the CPU
2
C bus format.
2
C bus
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