DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 233
![MCU 16BIT FLASH 3V 512K 144-TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.3
Port 3 is an 8-bit I/O port. Port 3 pins also function as a bidirectional data bus, wake-up event
input pins. Port 3 functions change according to the operating mode. Port 3 has the following
registers.
• Port 3 data direction register (P3DDR)
• Port 3 data register (P3DR)
• Port 3 pull-up MOS control register (P3PCR)
8.3.1
The individual bits of P3DDR specify input or output for the pins of port 3.
8.3.2
P3DR stores output data for the port 3 pins.
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
P37DDR
P36DDR
P35DDR
P34DDR
P33DDR
P32DDR
P31DDR
P30DDR
Bit Name
P37DR
P36DR
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
Port 3
Port 3 Data Direction Register (P3DDR)
Port 3 Data Register (P3DR)
0
0
0
0
0
0
0
0
Initial Value
Initial Value
0
0
0
0
0
0
0
0
R/W Description
W
W
W
W
W
W
W
W
R/W Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
In normal extended mode:
Bidirectional data bus
In other mode:
The corresponding port 3 pins are output ports when
the P3DDR bits are set to 1, and input ports when
cleared to 0.
In normal extended mode (ADMXE = 0):
If a port 3 read is performed while the P3DDR bits are
set to 1, the P3DR values are read. When the P3DDR
bits are cleared to 0, 1 is read.
In other mode:
If a port 3 read is performed while the P3DDR bits are
set to 1, the P3DR values are read. If a port 3 read is
performed while the P3DDR bits are cleared to 0, the
pin states are read.
Rev. 3.00, 03/04, page 191 of 830
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