DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 497

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.3.7
ICSR consists of status flags. Also see tables 15.4 and 15.5.
Bit
7
6
5
Bit Name
ESTP
STOP
IRTR
I
2
C Bus Status Register (ICSR)
Initial
Value
0
0
0
R/W
R/(W)* Error Stop Condition Detection Flag
R/(W)* Normal Stop Condition Detection Flag
R/(W)* I
Description
This bit is valid in I
[Setting condition]
When a stop condition is detected during frame transfer.
[Clearing conditions]
This bit is valid in I
[Setting condition]
When a stop condition is detected after frame transfer is
completed.
[Clearing conditions]
Flag
Indicates that the I
request to the CPU, and the source is completion of
reception/transmission of one frame in continuous
transmission/reception for which DTC activation is
possible. When the IRTR flag is set to 1, the IRIC flag is
also set to 1 at the same time.
[Setting conditions]
I
I
format mode:
[Clearing conditions]
2
2
2
C Bus Interface Continuous Transfer Interrupt Request
C bus format slave mode:
C bus format master mode or clocked synchronous serial
When 0 is written in ESTP after reading ESTP = 1
When the IRIC flag in ICCR is cleared to 0
When 0 is written in STOP after reading STOP = 1
When the IRIC flag is cleared to 0
When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
When the ICDRE or ICDRF flag is set to 1
When 0 is written after reading IRTR = 1
When the IRIC flag is cleared to 0 while ICE is 1
2
2
2
C bus format slave mode.
C bus format slave mode.
C bus interface has issued an interrupt
Rev. 3.00, 03/04, page 455 of 830

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