DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 214
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 7.9
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from on-chip ROM to an internal I/O register, then the time required for the
DTC operation is 13 states. The time from activation to the end of data write is 10 states.
Rev. 3.00, 03/04, page 172 of 830
Object to be Accessed
Bus width
Access states
Execution
status
Vector read
Register
information
read/write
Byte data read S
Word data read
Byte data write S
Word data write
Internal operation
Number of States Required for Each Execution Status
S
S
S
S
S
M
K
K
J
L
L
I
On-Chip RAM
(H'FFEC00 to
H'FFEFFF)
32
1
—
1
1
1
1
1
1
I
+ Σ (J · S
On-Chip RAM
(On-chip RAM area
other than H'FFEC00 to
H'FFEFFF)
16
1
—
—
1
1
1
1
1
J
+ K · S
K
+ L · S
On-
Chip
ROM
16
1
1
—
1
1
1
1
1
L
) + M · S
On-Chip
I/O
Registers
8
2
—
—
2
4
2
4
1
16
2
—
—
2
2
2
2
1
M
External Devices
8
2
4
—
2
4
2
4
1
8
3
6 + 2m
—
3 + m
6 + 2m
3 + m
6 + 2m
1
16
2
2
—
2
2
2
2
1
16
3
3 + m
—
3 + m
3 + m
3 + m
3 + m
1
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