DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 516

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Receive Operation Using the Wait Function:
Figures 15.13 and 15.14 show the sample flowcharts for the operations in master receive mode
(WAIT = 1).
Rev. 3.00, 03/04, page 474 of 830
Figure 15.13 Sample Flowchart for Operations in Master Receive Mode
No
No
No
Set BBSY= 0 and SCP= 0
Wait for one clock pulse
Set HNDS = 0 in ICXR
Set ACKB = 0 in ICSR
Set WAIT = 1 in ICMR
Set ACKB = 1 in ICSR
Set WAIT = 0 in ICMR
Set TRS = 0 in ICCR
Master receive mode
Set TRS = 1 in ICCR
(receiving multiple bytes) (WAIT = 1)
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Last receive?
Read ICDR
Read ICDR
Read ICDR
Read ICDR
IRTR = 1?
IRIC = 1?
IRTR=1?
IRIC=1?
in ICCR
End
Yes
Yes
Yes
No
No
Yes
Yes
[16] Read the last receive data.
[17] Generate stop condition
[1] Select receive mode.
[2] Start receiving. The first read
[3] Wait for a receive wait
[5] Read the receive data.
[6] Clear IRIC.
[7] Set acknowledge data for the last reception.
[8] Wait for TRS setting
[9] Set TRS for stop condition issuance
[10] Read the receive data.
[11] Clear IRIC.
[12] Wait for a receive wait
[13] Determine end of reception
[14] Clear IRIC.
[15] Clear wait mode.
[4] Determine end of reception
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
is a dummy read.
(to end the wait insertion)
(to end the wait insertion)
Clear IRIC.
( IRIC should be cleared to 0
after setting WAIT = 0.)