DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 519
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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[13]
[14]
[15]
[16]
[17]
User processing
(master output)
(master output)
(slave output)
SDA
SCL
SDA
Master transmit mode
ICDR
IRTR
IRIC
Read the IRTR flag in ICSR.
If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop
condition.
If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state.
Execute step [12] to read the IRIC flag to detect the end of reception.
Clear the WAIT bit in ICMR to cancel the wait mode.
Clearing of the IRIC flag should be done while WAIT = 0. (If the WAIT bit is cleared to 0
after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the
stop condition may not be issued correctly.)
Read the last ICDR receive data.
Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when
SCL is high, and generates the stop condition.
[1] TRS cleared to 0
9
A
IRIC clear to 0
Figure 15.15 Master Receive Mode Operation Timing Example
Master receive mode
[2] ICDR read
Bit 7
(dummy read)
1
Bit 6
(MLS = ACKB = 0, WAIT = 1)
2
Bit 5
3
Data 1
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
[6] IRIC clear
(to end wait insertion)
8
[4]IRTR=0
[3]
Rev. 3.00, 03/04, page 477 of 830
A
[4] IRTR=1
9
[3]
[5] ICDR read
Bit 7
Data 1
(Data 1)
1
Bit 6
2
Data 2
[6] IRIC clear
Bit 5
3
Bit 4
4
Bit 3
5
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