DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 477
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
DF2166VT33WV
Manufacturer:
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DF2166VT33WV
Manufacturer:
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This LSI has a six-channel I
a subset of the Philips I
controls the I
15.1
• Selection of addressing format or non-addressing format
• Conforms to Philips I
• Two ways of setting slave address (I
• Start and stop conditions generated automatically in master mode (I
• Selection of acknowledge output levels when receiving (I
• Automatic loading of acknowledge bit when transmitting (I
• Wait function in master mode (I
• Wait function (I
• Interrupt sources
• Selection of 32 internal clocks (in master mode)
• Direct bus drive
IFIIC50C_000020030700
I
Clocked synchronous serial format: non-addressing format without acknowledge bit, for
A wait can be inserted by driving the SCL pin low after data transfer, excluding
The wait can be cleared by clearing the interrupt flag.
A wait request can be generated by driving the SCL pin low after data transfer.
The wait request is cleared when the next transfer becomes possible.
Data transfer end (including when a transition to transmit mode with I
Address match: when any slave address matches or the general call address is received in
Arbitration loss
Start condition detection (in master mode)
Stop condition detection (in slave mode)
PinsSCL0 to SCL5 and SDA0 to SDA5 (normally NMOS push-pull outputs) function
master operation only
acknowledgement.
when ICDR data is transferred, or during a wait state)
slave receive mode with I
arbitration)
as NMOS open-drain outputs when the bus drive function is selected.
2
C bus format: addressing format with acknowledge bit, for master/slave operation
Features
2
C bus differs partly from the Philips configuration, however.
2
C bus format)
Section 15 I
2
C bus (inter-IC bus) interface functions. The register configuration that
2
C bus interface (I
2
C bus interface (IIC). The I
2
C bus format (including address reception after loss of master
2
C bus format)
2
C bus format)
2
2
C Bus Interface (IIC)
C bus format)
2
C bus interface conforms to and provides
2
C bus format)
2
C bus format)
Rev. 3.00, 03/04, page 435 of 830
2
C bus format)
2
C bus format occurs,
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