DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 578
![MCU 16BIT FLASH 3V 512K 144-TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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16.3.10 SERIRQ Control Register 0 (SIRQCR0)
The SIRQCR0 register contains status bits that indicate the SERIRQ operating mode and status
bits that specify SERIRQ0 interrupt sources.
The SIRQCR0 register is initialized to H'00 by a reset or in hardware standby mode.
Rev. 3.00, 03/04, page 536 of 830
Bit
7
6
5
Bit Name Initial Value Slave Host Description
Q/C
SELREQ 0
IEDIR
0
0
R
R/W
R/W
R/W
Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end
of an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
•
•
1: Quiet mode
[Setting condition]
•
Start Frame Initiation Request Select
Specifies the condition of start frame activation when
the host interrupt request is cleared in quiet mode.
0: When all host interrupt requests are cleared in
1: When at least one host interrupt request is
Interrupt Enable Direct Mode
Specifies whether LPC channel 2 SERIRQ interrupt
source (SMI, HIRQ6, HIRQ9 to HIRQ11) generation
is conditional upon OBF, or is controlled only by the
host interrupt enable bit.
0: Host interrupt is requested when host interrupt
1: Host interrupt is requested when host interrupt
quiet mode, start frame initiation is requested
cleared in quiet mode, start frame initiation is
requested
enable bit and corresponding OBF are both set to
1
enable bit is set to 1
LPC hardware reset, LPC software reset
Specification by the stop frame of the SERIRQ
transfer cycle
Specification by the stop frame of the SERIRQ
transfer cycle
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