DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 532
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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DF2166VT33WV
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15.4.8
This LSI provides the DTC to allow continuous data transfer. IIC_4 and IIC_5 cannot use the
DTC. The DTC is initiated when the IRTR flag is set to 1, which is one of the two interrupt flags
(IRTR and IRIC). When the ACKE bit is 0, the ICDRE, IRIC, and IRTR flags are set at the end of
data transmission regardless of the acknowledge bit value. When the ACKE bit is 1, the ICDRE,
IRIC, and IRTR flags are set if data transmission is completed with the acknowledge bit value of
0, and when the ACKE bit is 1, only the IRIC flag is set if data transmission is completed with the
acknowledge bit value of 1.
When initiated, DTC transfers specified number of bytes, clears the ICDRE, IRIC, and IRTR flags
to 0. Therefore, no interrupt is generated during continuous data transfer; however, if data
transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, DTC is
not initiated, thus allowing an interrupt to be generated if enabled.
Rev. 3.00, 03/04, page 490 of 830
When FS = 1 and FSX = 1 (clocked synchronous serial format)
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
SCL
SDA
IRIC
User processing
SCL
SDA
IRIC
User processing
Operation Using the DTC
7
7
7
7
Figure 15.27 IRIC Setting Timing and SCL Control (3)
8
8
8
8
1
1
Clear IRIC
Clear IRIC
2
2
Write to ICDR (transmit)
or read from ICDR (receive)
3
3
1
4
1
4
Clear IRIC
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