DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 557
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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• HICR1
Bit
7
6
Bit Name Initial Value Slave Host Description
LPCBSY
CLKREQ 0
0
R
R
R/W
LPC Busy
Indicates that the LPC interface is processing a
transfer cycle.
0: LPC interface is in transfer cycle wait state
•
•
[Clearing conditions]
•
•
•
•
1: LPC interface is performing transfer cycle
[Setting condition]
•
LCLK Request
Indicates that the LPC interface's SERIRQ output is
requesting a restart of LCLK.
0: No LCLK restart request
[Clearing conditions]
•
•
•
•
1: LCLK restart request issued
[Setting condition]
•
processing
Bus idle, or transfer cycle not subject to
processing is in progress
Cycle type or address indeterminate during
transfer cycle
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software
shutdown
Forced termination (abort) of transfer cycle
subject to processing
Normal termination of transfer cycle subject to
processing
Match of cycle type and address
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software
shutdown
SERIRQ is set to continuous mode
There are no further interrupts for transfer to the
host in quiet mode
In quiet mode, SERIRQ interrupt output becomes
necessary while LCLK is stopped
Rev. 3.00, 03/04, page 515 of 830
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