DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 139

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.5
The DTC can be activated by an interrupt. In this case, the following options are available:
• Interrupt request to CPU
• Activation request to DTC
• Both of the above
For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer
Controller (DTC). Figure 5.9 shows a block diagram of the DTC and interrupt controller.
The interrupt controller has three main functions in DTC control.
Selection of Interrupt Source: It is possible to select DTC activation request or CPU interrupt
request with the DTCE bit of DTCERA to DTCERE in the DTC. After a DTC data transfer, the
DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the
specification of the DISEL bit of MRB in the DTC. When the DTC performs the specified number
of data transfers and the transfer counter reaches 0, following the DTC data transfer the DTCE bit
is cleared to 0 and an interrupt request is sent to the CPU.
Determination of Priority: The DTC activation source is selected in accordance with the default
priority order, and is not affected by mask or priority levels. See section 7.5, Location of Register
Information and DTC Vector Table, for the respective priorities.
peripheral
interrupt
On-chip
module
IRQ
DTC Activation by Interrupt
Interrupt source
clear signal
Interrupt
request
Interrupt controller
Figure 5.9 Interrupt Control for DTC
Selection
DTVECR
DTCER
circuit
Select
signal
clear signal
Clear signal
SWDTE
Determination of
Control logic
priority
Rev. 3.00, 03/04, page 97 of 830
CPU interrupt
request vector
number
DTC activation
request vector
number
Clear signal
I, UI
DTC
CPU