DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 533
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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The acknowledge bit may indicate specific events such as completion of receive data processing
for some receiving devices, and for other receiving devices, the acknowledge bit may be held to 1,
indicating no specific events.
The I
the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out
in conjunction with CPU processing by means of interrupts.
Table 15.9 shows some examples of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Table 15.9 Examples of Operation Using the DTC
Item
Slave address +
R/W bit
transmission/
reception
Dummy data
read
Actual data
transmission/
reception
Dummy data
(H'FF) write
Last frame
processing
Transfer request
processing after
last frame
processing
Setting of
number of DTC
transfer data
frames
2
C bus format provides for selection of the slave device and transfer direction by means of
Master Transmit
Mode
Transmission by
DTC (ICDR write)
Transmission by
DTC (ICDR write)
Not necessary
1st time: Clearing
by CPU
2nd time: Stop
condition issuance
by CPU
Transmission:
Actual data count
+ 1 (+1 equivalent
to slave address +
R/W bits)
Master Receive
Mode
Transmission by
CPU (ICDR write)
Processing by
CPU (ICDR read)
Reception by
DTC (ICDR read)
Reception by
CPU (ICDR read)
Not necessary
Reception: Actual
data count
Slave Transmit
Mode
Reception by
CPU (ICDR read)
Transmission by
DTC (ICDR write)
Processing by
DTC (ICDR write)
Not necessary
Automatic clearing
on detection of
stop condition
during
transmission of
dummy data (H'FF)
Transmission:
Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Rev. 3.00, 03/04, page 491 of 830
Slave Receive
Mode
Reception by CPU
(ICDR read)
Reception by DTC
(ICDR read)
Reception by CPU
(ICDR read)
Not necessary
Reception: Actual
data count
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