DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 836
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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25.3.3
Table 25.8 shows the bus timing. In subclock (φSUB = 32.768 kHz) operation, external expansion
mode operation cannot be guaranteed.
Table 25.8 Bus Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Rev. 3.00, 03/04, page 794 of 830
Item
Address delay time
Address setup time
Address hold time
CS delay time (IOS,
CS256, CPCS1)
AS delay time
RD delay time 1
RD delay time 2
Read data setup time
Read data hold time
Read data access time 1 t
Read data access time 2 t
Read data access time 3 t
Read data access time 4 t
Read data access time 5 t
WR delay time 1
WR delay time 2
WR pulse width 1
WR pulse width 2
Write data delay time
Write data setup time
Write data hold time
WAIT setup time
WAIT hold time
Bus Timing
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AD
AS
AH
CSD
ASD
RSD1
RSD2
RDS
RDH
ACC1
ACC2
ACC3
ACC4
ACC5
WRD1
WRD2
WSW1
WSW2
WDD
WDS
WDH
WTS
WTH
Min.
0.5 × t
0.5 × t
10
15
0
1.0 × t
20
1.5 × t
20
0
0.5 × t
25
5
cyc
cyc
cyc
cyc
cyc
–15
–
–
–
– 5
Max.
15
15
15
15
15
1.0 × t
1.5 × t
2.0 × t
2.5 × t
3.0 × t
15
15
25
cyc
cyc
cyc
cyc
cyc
– 30
– 25
– 30
– 25
– 30
Unit
ns
Test Conditions
Figures 25.12 to 25.16
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