DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 409
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Notes: 1. Only 0 can be written, to clear the flag.
Bit
3
2
1
0
2. etu: Element Time Unit (time taken to transfer one bit)
Bit Name
PER
TEND
MPB
MPBT
Initial Value
0
1
0
0
R/W
R/(W)*
R
R
R/W
1
Description
Parity Error
[Setting condition]
When a parity error is detected during reception
[Clearing condition]
When 0 is written to PER after reading PER = 1
Transmit End
TEND is set to 1 when the receiving end
acknowledges no error signal and the next transmit
data is ready to be transferred to TDR.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
Not used in smart card interface mode.
Multiprocessor Bit Transfer
Write 0 to this bit in smart card interface mode.
When GM = 0 and BLK = 0, 2.5 etu*
transmission start
When GM = 0 and BLK = 1, 1.5 etu*
transmission start
When GM = 1 and BLK = 0, 1.0 etu*
transmission start
When GM = 1 and BLK = 1, 1.0 etu*
transmission start
When both TE in SCR and ERS are 0
When ERS = 0 and TDRE = 1 after a specified
time passed after the start of 1-byte data
transfer. The set timing depends on the register
setting as follows.
When 0 is written to TDRE after reading
TDRE = 1
When a TXI interrupt request is issued allowing
DTC to write the next data to TDR
Rev. 3.00, 03/04, page 367 of 830
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2
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2
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