DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 201

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.3
To count events of EVENT 0 to EVENT15 by the DTC event counter function, set DTC as below.
Table 7.2
The corresponding flag to ECS input pin is set to 1 when the event pins that are specified by the
ECSB3 to ECSB0 in ECCR detect the edge events specified by the EDSB in ECCR. For this flag
state, status/address codes are generated.
An EVENTI interrupt request is generated even if only one bit in ECS is set to 1.
The EVENTI interrupt request activates the DTC and transfers data from RAM to RAM in the
same address. Data is incremented in the DTC. The lower five bits of SAR and DAR are replaced
with address code that is generated by the ECS flag status.
Register
MRA
MRB
SAR
DAR
CRAH
CRAL
CRBH
CRBL
DTCERC
KBCOMP
RAM
DTC Event Counter
7, 6
5, 4
3, 2
1
0
7
6
5 to 0
23 to 0
23 to 0
7 to 0
7 to 0
7 to 0
7 to 0
4
7

Bit
DTC Event Counter Conditions
Bit Name
SM1, SM0 00: SAR is fixed.
DM1, DM0 00: DAR is fixed.
MD1, MD0 01: Repeat mode
DTS
Sz
CHNE
DISEL







DTCEC4
EVENTE

Description
0: Destination is repeat area
1: Word size transfer
0: Chain transfer is disabled
0: Interrupt request is generated when data is transferred by
B'000000
Identical optional RAM address. Its lower five bits are B'00000.
The start address of 16 words is this address. They are
incremented every time an event is detected in EVENT0 to
EVENT15.
H'FF
H'FF
H'FF
H'FF
1: DTC function of the event counter is enabled
1: Event counter enable
(SAR, DAR) : Result of EVENT0 count
(SAR, DAR) + 2: Result of EVENT 1 count
(SAR, DAR) + 4: Result of EVENT 2 count
(SAR, DAR) + 30: Result of EVENT 15 count
the number of specified times
↓
Rev. 3.00, 03/04, page 159 of 830