DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 574
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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• STR3
Rev. 3.00, 03/04, page 532 of 830
Bit
7
6
5
(When TWRE = 1 or SELSTR3 = 0)
IBF3B
OBF3B
MWMF
Bit Name Initial Value Slave Host Description
0
0
0
R
R/(W)* R
R
R/W
R
R
Bidirectional Data Register Input Data Full
Indicates whether or not there is receive data in
TWR0 to TWR15. This is an internal interrupt source
to the slave processor (this LSI).
0: There is not receive data in TWR15
[Clearing condition]
When the slave processor reads TWR15
1: There is receive data in TWR0 to TWR15
[Setting condition]
When the host processor writes to TWR15 using I/O
write cycle
Bidirectional Data Register Output Data Full
Indicates whether or not there is transmit data in
TWR0 to TWR15.
0: There is not transmit data in TWR15
[Clearing condition]
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
OBF3B bit
1: There is transmit data in TWR0 to TWR15
[Setting condition]
When the slave processor writes to TWR15
Master Write Mode Flag
Indicates that master write mode is entered by
writing to TWR0 from the host processor.
0: [Clearing condition]
When the slave processor reads TWR15
1: [Setting condition]
When the host processor writes to TWR0 using I/O
write cycle while SWMF = 0
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