DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 830
DF2166VT33WV
Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VT33WV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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25.3
Figure 25.3 shows the test conditions for the AC characteristics.
25.3.1
Table 25.4 shows the clock timing. The clock timing specified here covers clock output (φ) and
clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization
times. For details of external clock input (EXTAL pin and EXCL pin) timing, see table 25.5 and
25.6.
Table 25.4 Clock Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Rev. 3.00, 03/04, page 788 of 830
Item
Clock cycle time
Clock high level pulse
width
Clock low level pulse width t
Clock rise time
Clock fall time
Reset oscillation
stabilization (crystal)
Software standby
oscillation stabilization time
(crystal)
AC Characteristics
Clock Timing
LSI output pin
t
Symbol
t
t
t
t
t
cyc
CH
CL
Cr
Cf
OSC1
OSC2
Figure 25.3 Output Load Circuit
C
R
Min.
30
10
10
10
8
H
3 V
R
L
Max.
200
5
5
C = 30pF : All ports
R
R
I/O timing test levels
• Low level
• High level
L
H
= 2.4 kΩ
= 12 kΩ
: 0.8 V
: 1.5 V
Unit
ns
ms
Reference
Figure 25.4
Figure 25.5
Figure 25.6
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