MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 103

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

RMCST—RMC Cycle Special Treatment
EMWS—External Master Wait State (EMWS);
ADCE—Address Decode Conflict Enable
BCLM—Bus Clear Mask
MOTOROLA
The assertion of the RMC by the M68000 core is seen by the arbiter and will prevent the
arbiter from issuing bus grants until the completion of M68000-initiated locked read-mod-
ify-write activity. After system reset, this bit defaults to zero.
When EMWS is set and an external master is using the chip-select logic for DTACK gen-
eration or is synchronously reading from the internal peripherals (SAM = 1), one additional
wait state will be inserted in external master cycle to external memory and peripherals and
also in every cycle from the external master to MC68302 internal memory and peripherals.
When EMWS is cleared, all synchronous internal accesses will be with zero wait states,
and the chip-select logic will generate DTACK after the exact programmed number of wait
states. The chip-select lines are asserted slightly earlier for internal master memory cy-
cles than for an external master. EMWS should be set whenever these timing differences
will necessitate an additional wait state for external masters. After system reset, this bit
defaults to zero.
After system reset, this bit defaults to zero.
0 = The locked read-modify-write cycles of the TAS instruction will be identical to the
1 = The MC68302 uses RMC to negate AS and CS at the end of the read portion of
0 = BERR is not asserted by a conflict in the chip-select logic when two or more chip-
1 = BERR is asserted by a conflict in the chip-select logic when two or more chip-select
0 = The arbiter does not use the M68000 core internal IPEND signal to assert the in-
1 = The arbiter uses the M68000 core internal IPEND signal to assert the internal and
M68000 (AS and CS will be asserted during the entire cycle). The arbiter will issue
BG, regardless of the M68000 core RMC. If an IMP chip select is used, the DTACK
generator will insert wait states on the read cycle only.
the RMC cycle and reasserts AS and CS at the beginning of the write portion. BG
will not be asserted until the end of the write portion. If an IMP chip select is used,
the DTACK generator will insert wait states on both the read and write portion of
the cycles.
select lines are programmed to overlap the same area.
lines are programmed to overlap the same area.
ternal and external bus clear signals.
external bus clear signals.
WPV will be set, regardless of the value of WPVE.
ADC will be set, regardless of the value of ADCE.
MC68302 USER’S MANUAL
NOTE
NOTE
System Integration Block (SIB)
3-53