MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 413

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

A synchronized setting of the ENT bit causes the transmit FIFO to be filled in a fixed time if
the following two conditions are true: 1) the SDMA is the highest priority bus master in the
system (i.e., there is no external bus master during this period) and 2) the SCC needed for
the transmission is the only SCC currently being used. Both of these factors become negli-
gible if the serial clock rate is much slower than the system clock rate (e.g., a 1 to 50 ratio).
(A slow serial clock rate means that deviations are much less than a serial bit time and have
no effect on transmission delay.)
The preceding example showed ENT being set before the time slot. If there are more than
36 serial clocks following the setting of the ENT bit, it is possible to set the ENT bit during
the time slot and see the same behavior. The assertion of the RTS signal can be used to
verify that a sufficient number of clocks occurred after the setting of ENT.
In the transparent operation, assertion of RTS1 is slightly different from that of RTS2 and
RTS3. The description of RTS in Table D-4, the text on D-73, Figure D-29, and the text on
D-74 is correct for RTS2 and RTS3, but not exactly correct for RTS1. RTS1 has the opposite
polarity in PCM mode. RTS1 goes low when SIMODE is programmed as the PCM mode,
and then goes high when the SCC is about ready to transmit.
If the time slots are not long enough to guarantee transmission after the second time slot,
then the synchronized setting of the ENT bit should at least guarantee a fixed delay to the
start of data. In this case, there will be additional time slots with $FF data until the data1 byte
is transmitted.
MOTOROLA
SOMETIME IN THE PAST:
1. STOP TRANSMIT COMMAND
2. CLEAR ENT
3. RESTART TRANSMIT COMMAND
4. SET READY BIT ON NEXT TX BD
DATA
FF'S
RX
GENERATE INTERRUPT TO M68000
CORE HERE, AND SET ENT BIT.
Figure D-30. PCM Transmission Timing Technique
RX DATA
FF'S
RTS ASSERTED BY SCC HERE.
AFTER THIS POINT, THE NEXT RISING
SYNC CAUSES TRANSMISSION.
MC68302 USER’S MANUAL
RISING SYNC OCCURS
HERE.
TX BUFFER DATA BEGINS
AFTER ONE FF.
FF-DATA1-DATA2-DATA3...
(CLOCK NOT TO SCALE)
RX DATA
MC68302 Applications
L1TXD
L1RXD
L1CLK
L1SY0
L1SY1
RTS2 or RTS3
(RTS2 active high
IN PCM MODE)
D-63