MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 228

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
Error Counters
4.5.14.9 DDCMP Mode Register
Each SCC mode register is a 16-bit, memory- mapped, read-write register that controls the
SCC operation. The term DDCMP mode register refers to the protocol-specific bits (15–6)
of the SCC mode register when that SCC is configured for DDCMP. The read-write DDCMP
mode register is cleared by reset.
NOS3–NOS0—Minimum Number of SYN1—SYN2 Pairs between or before Messages
(1 to 16 SYNC Pairs)
4-108
NOS3
6. Parity Error. When a parity error occurs, the channel writes the received character to
The CP maintains four 16-bit (modulo 2**16) error counters for each DDCMP controller.
They can be initialized by the user when the channel is disabled. The counters are as fol-
lows:
If NOS3–NOS0 = 0000, then 1 SYNC pair will be transmitted; if NOS3–NOS0 = 1111, then
16 SYNC pairs will be transmitted.
15
—CRC1EC—CRC1 Error Counter
—CRC2EC—CRC2/CRC3 Error Counter
—NMARC — Nonmatching Address Received Counter (updated only when the frame
—DISMC — Discarded Messages (received messages when there are no free buffers
The channel will enter hunt mode immediately. It is possible that a SYN1–SYN2-
(SOH,DLE,ENQ) sequence in data will be incorrectly interpreted as the start of the
next header, but this “header” will have a CRC error.
the buffer, closes the buffer, sets the parity error (PR) bit in the BD, and generates the
RBK interrupt (if enabled).
The channel will enter hunt mode immediately. It is possible that a SYN1–SYN2-
(SOH,DLE,ENQ) sequence in data will be incorrectly interpreted as the start of the
next header, but this “header” will have a CRC error.
is error-free)
NOS2
14
and the frame is error-free)
This error can occur only on asynchronous links.
This error can occur only on asynchronous links.
With appropriate programming of the transmit BD (TC = 1 and L
= 0), it is possible to transmit back-to-back messages.
NOS1
13
NOS0
12
11
—
MC68302 USER’S MANUAL
V.110
10
NOTE
NOTE
NOTE
—
9
—
8
SYNF
7
ENC
6
5
COMMON SCC MODE BITS
MOTOROLA
0