MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 439
![IC MPU MULTI-PROTOCOL 132-PQFP](/photos/6/76/67684/mc68302eh16c_sml.jpg)
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 439 of 481
- Download datasheet (2Mb)
E.2.1.1 COMMUNICATIONS PROCESSOR (CP) REGISTERS. The CP has one set of
three registers that configure the operation of the serial interface for all three SCCs. These
registers are discussed in the next three subsections.
E.2.1.1.1 Command Register (CR). The command register is an 8-bit register located at
offset $860 (on D15-D8 of a 16-bit data bus). This register is used to issue commands to the
CP. The user should set the FLG bit when a command is written to the command register.
The CP clears the FLG bit during command processing to indicate that it is ready for the next
command.
RST—Software Reset Command (set by the user and cleared by the CP)
GCI—GCI Commands
OPCODE—Command Opcode
BIT 3—Reserved (should be set to zero by the user when the command register is written)
CH. NUM.—Channel Number
FLG—Command Semaphore Flag (set by the user and cleared by the CP upon command
completion)
MOTOROLA
0 = No software reset command issued or cleared by CP during software reset se-
1 = Software reset command (FLG bit should also be set if it is not already set).
0 = Normal operation.
1 = The OPCODE bits are used for GCI commands (user should set CH. NUM. to 10
00 = STOP TRANSMIT Command.
01 = RESTART TRANSMIT Command.
10 = ENTER HUNT MODE Command.
11 = Reset receiver BCS generator (used only in BISYNC mode).
00 = SCC1.
01 = SCC2.
10 = SCC3.
11 = Reserved.
0 = CP is ready to receive a new command (should be checked before issuing the next
1 = Command register contains a command to be executed or one that is currently be-
quence.
and FLG to 1).
command to the CP).
ing executed.
RST
7
GCI
6
MC68360 USER’S MANUAL
5
OPCODE
4
—
3
CH. NUM.
2
1
FLG
SCC Programming Reference
0
E-17
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