MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 416

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MC68302 Applications
D-66
6. Setting SCCE2 to $FF clears out any current status in the event register. SCCE2 =
7. You must indicate in the SCCM2 register which (if any) transparent events you wish
8. Setting IMR to $0400 allows interrupts from SCC2 to be enabled in the interrupt con-
9. Initialize the receive and transmit function codes to 000, and set the receive buffer size
10. Initialize the BISYNC parameters. These parameters do not involve transparent mode;
11. The Tx BD buffer starts at address $30000. It is 18 (hex) bytes long. (Notice that the
12. Two empty Rx BDs are needed to receive the transmit frame. Both are currently emp-
using transparent mode with the EXSYN bit set in SCM2.
DSR2 = $7E7E
$FF
to cause interrupts. Bit 5 should be set to zero. Bit 3 is only valid in BISYNC mode and
has no meaning in transparent mode. All other bits are valid. For this example, we will
disable interrupts, but all events will still be set in SCCE2.
SCCM2 = $00
troller; however, since SCCM2 = $00, any SCC2 interrupt requests are prevented
from reaching the interrupt controller, and this step has no effect.
IMR = $0400
to 10 (hex) bytes. These are the general-purpose parameter RAM values forSCC2.
RFCR = $00
TFCR = $00
MRBLR = $0010
however, it is a good idea to initialize them in case BISYNC mode is ever accidental-
ly entered by clearing the NTSYN bit in SCM2. The values for BSYNC and BDLE are
arbitrary and were chosen so that the two registers have different values. The control
characters table is disabled for good measure, although this too is not used in trans-
parent mode.
PRCRC = $0000
PTCRC = $0000
PAREC = $0000
BSYNC = $0033
BDLE = $0044
CHARACTER1 = $8000
MRBLR value equal to $0010 does not restrict the transmit buffer size.) The status
$D800 says that the buffer is ready and in external RAM. Since the I bit is set, the TX
bit in the SCCE2 register will be set upon completion, and this is the “last” buffer in
this transmission. The next Tx BD is set up so that it is not ready; transmission will
halt after one Tx BD.
Tx BD = $D800 $0018 $0003 $0000
Tx BD = $5800 $xxxx $xxxx $xxxx (This Tx BD is not yet ready.)
ty, and data is to be stored in external RAM buffers. Since the I bits are set, the RX bit
in the SCCE2 register will be set when each buffer is filled with data. The third Rx BD
is not ready yet. If it was ready, it would be filled with all $FFs (idles) after the first two
buffers were filled.
Rx BD = $D000 $0000 $0004 $0000
Rx BD = $D000 $0000 $0004 $0010
MC68302 USER’S MANUAL
MOTOROLA