MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 221

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

By setting its SCC mode register (SCM), any of the SCC channels may be configured to
function as a DDCMP controller. The DDCMP link can be either synchronous (by program-
ming the MODE1–MODE0 bits of the SCC mode register to DDCMP) or asynchronous (by
programming the MODE1–MODE0 bits of the SCC mode register to asynchronous and set-
ting the DDCMP bit in the UART mode register). The DDCMP controller handles the basic
functions of the DDCMP protocol in both cases.
The SCC in DDCMP mode can work in either IDL, GCI, PCM highway, or NMSI interfaces.
When the SCC is used with a modem interface (NMSI), the serial outputs are connected di-
rectly to the external pins. The modem interface uses seven dedicated pins: transmit data
(TXD), receive data (RXD), receive clock (RCLK), transmit clock (TCLK), carrier detect
(CD), clear to send (CTS), and request to send (RTS). Other modem lines can be supported
through the parallel I/O pins.
The DDCMP controller consists of separate transmit and receive sections whose operations
are asynchronous with the M68000 core and may be either synchronous or asynchronous
with respect to the other SCCs. Each clock can be supplied either from the baud rate gen-
erator or externally. More information on the baud rate generator is available in 4.5.2 SCC
Configuration Register (SCON).
The DDCMP controller key features are as follows:
4.5.14.1 DDCMP Channel Frame Transmission Processing
The DDCMP transmitter is designed to work with almost no intervention from the M68000
core (see Figure 4-35).
When the M68000 core enables the DDCMP transmitter and the link is synchronous, it starts
transmitting SYN1–SYN2 pairs (programmed in the data synchronization register) or IDLEs
as determined in the DDCMP mode register. The DDCMP controller polls the first buffer de-
scriptor (BD) in the channel's transmit BD table. When there is a message to transmit, the
DDCMP controller fetches the data from memory and starts transmitting the message (after
first transmitting the SYN1–SYN2 pair when the link is synchronous).
MOTOROLA
• Synchronous or Asynchronous DDCMP Links Supported
• Flexible Data Buffers
• Four Address Comparison Registers with Mask
• Automatic Frame Synchronization
• Automatic Message Synchronization by Searching for SOH, ENQ, or DLE
• CRC16 Generation/Checking
• NRZ/NRZI Data Encoding
• Maintenance of Four 16-Bit Error Counters
MC68302 USER’S MANUAL
Communications Processor (CP)
4-101