MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 89
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 89 of 481
- Download datasheet (2Mb)
When working in the MC68008 mode (BUSW is low), writing the high byte of TRR1 and
TRR2 will disable the timer's compare logic until the low byte is written.
TRR1 and TRR2 are set to all ones by reset. The reference value is not “reached” until TCN
increments to equal TRR.
3.5.2.3 Timer Capture Registers (TCR1, TCR2)
Each TCR is a 16-bit register used to latch the value of the counter during a capture opera-
tion when an edge occurs on the respective TIN1 or TIN2 pin. TCR1 and TCR2 appear as
memory-mapped read-only registers to the user.
When working in the MC68008 mode (BUSW is low), reading the high byte of TCR1 and
TCR2 will disable the timer's capture logic until the low byte is read.
TCR1 and TCR2 are cleared at reset.
3.5.2.4 Timer Counter (TCN1, TCN2)
TCN1 and TCN2 are 16-bit up-counters. Each is memory-mapped and can be read and writ-
ten by the user. A read cycle to TCN1 and TCN2 yields the current value of the timer and
does not affect the counting operation.
When working in the MC68008 mode (BUSW is low), reading the high byte of TCN1 and
TCN2 will latch the low byte into a temporary register; a subsequent read cycle on the low
byte yields the value of the temporary register.
A write cycle to TCN1 and TCN2 causes both the counter register and the corresponding
prescaler to be reset to zero. In MC68008 mode (BUSW is low), a write cycle to either the
high or low byte of the TCN will reset the counter register and the corresponding prescaler
to zero.
3.5.2.5 Timer Event Registers (TER1, TER2)
Each TER is an 8-bit register used to report events recognized by any of the timers. On rec-
ognition of an event, the timer will set the appropriate bit in the TER, regardless of the cor-
responding interrupt enable bits (ORI and CE) in the TMR. TER1 and TER2, which appear
to the user as memory-mapped registers, may be read at any time.
A bit is cleared by writing a one to that bit (writing a zero does not affect a bit's value). More
than one bit may be cleared at a time. Both bits must be cleared before the timer will negate
the INRQ to the interrupt controller. This register is cleared at reset.
CAP—Capture Event
MOTOROLA
The counter value has been latched into the TCR. The CE bits in the TMR are used to
enable the interrupt request caused by this event.
7
MC68302 USER’S MANUAL
RESERVED
2
REF
1
System Integration Block (SIB)
CAP
0
3-39
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