MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 241
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
W—Wrap (Final BD in Table)
I—Interrupt
L—Last
Bit 10—Must be set to zero by the user.
Bits 9–2, 0—Reserved for future use.
UN—Underrun
Data Length
Tx Buffer Pointer
4.5.15.9 V.110 Event Register
The SCC event register (SCCE) is referred to as the V.110 event register when the SCC is
configured as a V.110 controller. It is an 8-bit register used to report events recognized by
the V.110 channel and to generate interrupts. On recognition of an event, the V.110 control-
MOTOROLA
The following bits are written by the V.110 controller after it has finished transmitting the
associated data buffer.
The V.110 controller encountered a transmitter underrun condition while transmitting the
associated data buffer.
The data length is the number of octets that the V.110 controller should transmit from this
BD's data buffer. It is never modified by the CP. The data length should be greater than
zero.
This pointer, which contains the address of the associated data buffer, may be even or
odd. The buffer may reside in either internal or external memory.
0 = This is not the last BD in the Tx BD table.
1 = This is the last BD in the Tx BD table. After this buffer has been used, the V.110
0 = No interrupt is generated after this buffer has been serviced.
1 = Either TX or TXE in the V.110 event register will be set when this buffer has been
0 = This buffer is not the last in the message.
1 = This bit is set by the processor to indicate that this buffer is the last buffer in the
controller will transmit data from the first BD in the table.
serviced by the V.110 controller, which can cause interrupts.
current frame. The V.110 controller will transmit ones until the next BD is ready.
The user is required to set the wrap bit in one of the first eight
BDs; otherwise, errant behavior may occur.
For correct operation of the function codes, the upper 8 bits of
the pointer must be initialized to zero.
MC68302 USER’S MANUAL
NOTE
NOTE
Communications Processor (CP)
4-121
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