MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 265
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
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SECTION 5
SIGNAL DESCRIPTION
This section defines the MC68302 pinout. The input and output signals of the MC68302 are
organized into functional groups and are described in the following sections. The MC68302
is offered in a 132-pin (13 x 13) pin grid array (PGA), a 132-lead plastic quad flat package
(PQFP), and a 144-lead thin quad flat package (TQFP).
The MC68302 uses a standard M68000 bus for communication between both on-chip and
external peripherals. This bus is a single, continuous bus existing both on-chip and off-chip
the MC68302. Any access made internal to the device is visible externally. Any access
made external is visible internally. Thus, when the M68000 core accesses the dual-port
RAM, the bus signals are driven externally. Likewise, when an external device accesses an
area of external system memory, the chip-select logic can be used to generate the chip-se-
lect signal and DTACK.
5.1 FUNCTIONAL GROUPS
The input and output signals of the MC68302 are organized into functional groups as shown
in Table 5-1 and Figure 5-1.
MOTOROLA
Clocks
System Control
Address Bus
Data Bus
Bus Control
Bus Control
Bus Arbitration
Interrupt Control
NMSI1/ISDN I/F
NMSI2/PAIO
NMSI3/SCP/PAIO
IDMA/PAIO
IACK/PBIO
Timer/PBIO
PBIO
Functional Group
XTAL, EXTAL, CLKO
RESET, HALT, BERR, BUSW, DISCPU
A23–A1
D15–D0
AS, R/W, UDS/A0, LDS/DS, DTACK
RMC, IAC, BCLR
BR, BG, BGACK
IPL2–IPL0, FC2–FC0, AVEC
RXD, TXD, RCLK, TCLK, CD, CTS, RTS, BRG1
RXD, TXD, RCLK, TCLK, CD, CTS, RTS, SDS2
RXD, TXD, RCLK, TCLK, CD, CTS, RTS, PA12
DREQ, DACK, DONE
IACK7, IACK6, IACK1
TIN2, TIN1, TOUT2, TOUT1, WDOG
PB11–PB8
Table 5-1. Signal Definitions
MC68302 USER’S MANUAL
Signals
Number
23
16
3
5
5
3
3
7
8
8
8
3
3
5
4
5-1
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