MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 388

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MC68302 Applications
The interconnection between the MC68302 SCP and the MC145475 is straightforward. The
MC68302 is an SCP master device and will generate the clock timing and the
SCP_ENABLE for the SCP transaction. The SCP_EN signal is driven by a parallel output
pin and must be handled by software (asserted for each transaction between the MC68302
and the MC145475).
D.6.11 SCP Configuration
The SCP is configured by setting the SCP mode register. Setting the SCP mode register to
$2F will configure the SCP to the clock invert mode (clock is idle high, transmitted data is
shifted on falling edges and received bits are sampled on rising edges), and the internal
baud rate generator will divide the system clock by 32.
Each data transaction is triggered by setting the start bit high (after software has configured
the SCP buffer descriptor).
D.6.12 SCP Data Transactions
The MC145475 has two sets of read/write programmable registers. One is the nibble (4 bits)
register set and the other is the byte (8 bits) register set.
The registers are set to default value on reset. Read/write operation is made via the SCP
channel.
A byte register write is made by writing two bytes with the following format:
D-38
7
0
0
MC68302
1
1
1
1
SPRXD
SPCLK
SPTXD
PA7
1
1
Figure D-16. SCP Bus Interconnection
A3
A3
MC68302 USER’S MANUAL
A2
A2
A1
A1
SCP_EN[L]
SCP_CLK
SCP_TX
SCP_RX
A0
A0
0
A-3—A0 Address Register
A-3—A0 Address Register
SCP_EN
SCP_CLK
SCP_RX
SCP_TX
MC145475
MOTOROLA