MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 269

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.4 SYSTEM CONTROL
The system control pins are shown in Figure 5-3.
RESET
MOTOROLA
and system integration block. All M68000 bus timings are referenced to the CLKO signal.
CLKO supports both CMOS and TTL output levels. The output drive capability of the
CLKO signal is programmable in the CKCR register (see 3.9 Clock Control Register) to
one-third, two-thirds, or full strength, or this output can be disabled.
This bidirectional, open-drain signal, acting as an input and asserted along with the HALT
pin, starts an initialization sequence called a total system reset that resets the entire
MC68302. RESET and HALT should remain asserted for at least 100 ms at power-on re-
set, and at least 10 clocks otherwise. The on-chip system RAM is not initialized during re-
set except for several locations initialized by the CP.
An internally generated reset, from the M68000 RESET instruction, causes the RESET
line to become an output for 124 clocks. In this case, the M68000 core is not reset; how-
ever, the communication processor is fully reset, and the system integration block is al-
most fully reset (refer to Table 2-6 and Table 2-9 for a list of the unaffected registers). The
user may also use the RESET output signal in this case to reset all external devices.
During total system reset, the address, data, and bus control pins are all three-stated, ex-
cept for CS3–CS0, which are high, and IAC, which is low. The BG pin output is the same
as that on the BR input. The general-purpose I/O pins are configured as inputs, except for
WDOG, which is an open-drain output. The NMSI1 pins are all inputs, except for RTS1
and TXD1, which output a high value. RTS3, NC1, and NC3 are also high. CLKO is active
and BRG1 is CLO/3.
The RESET pin should not be asserted externally without also
asserting the HALT pin. To reset just the internal MC68302 pe-
ripherals, the RESET instruction may be used. If the RESET in-
struction is to be used, then the pull-up resistor on RESET
should not be greater than 1.2 k ohms.
Figure 5-3. System Control Pins
MC68302 USER’S MANUAL
MC68302
NOTE
BUSW
DISCPU
FRZ
RESET
HALT
BERR
Signal Description
5-5