MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 261
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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4.7.4.1 SMC1 Receive Buffer Descriptor
The CP reports information about the received byte using this (BD).
E—Empty
In GCI mode, when the IMP implements the monitor channel protocol, the IMP will wait until
this bit is set by the M68000 core before acknowledging the monitor channel data. In other
modes (transparent GCI and IDL), additional received data bytes will be discarded until the
empty bit is set by the M68000 core.
L—Last (EOM)
ER—Error Condition
MS—Data Mismatch
Bits 11–10—Reserved for future use.
AB—Received A Bit
EB—Received E Bit
Data—Data Field
MOTOROLA
This bit is valid only in GCI mode when the IMP implements the monitor channel protocol.
This bit is set when the end-of-message (EOM) indication is received on the E bit.
This bit is valid only in GCI mode when the IMP implements the monitor channel protocol
and the L bit is set. This bit is set when an error condition occurs on the monitor channel
protocol. A new byte is transmitted before the IMP acknowledges the previous byte.
This bit is valid only in GCI mode when the IMP implements the monitor channel protocol.
This bit is set when two different consecutive bytes are received and is cleared when the
last two consecutive bytes match. The IMP waits for the reception of two identical consec-
utive bytes before writing new data to the receive BD.
This bit is valid only in GCI mode when the monitor channel is in transparent mode.
This bit is valid only in GCI mode when the monitor channel is in transparent mode.
The data field contains the byte of data received by SMC1.
15
E
0 = This bit is cleared by the CP to indicate that the data byte associated with this BD
1 = This bit is set by the M68000 core to indicate that the data byte associated with this
is now available to the M68000 core.
BD is empty.
14
L
When this bit is set, the data byte is not valid.
13
ER
12
MS
11
MC68302 USER’S MANUAL
—
10
NOTE
AB
9
EB
8
7
Communications Processor (CP)
DATA
4-141
0
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