MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 403

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Figure D-24 shows the simplest NMSI receive case. NTSYN and EXSYN are set to enable
transparent mode. The choice of software operation in this case is irrelevant because the
CD (sync) pin is grounded externally, causing the SCC receiver to continuously receive da-
ta. As soon as the ENR bit in the SCM is set, bits begin being received into the SCC. Data
bits are sampled at every rising edge of RCLK, and no byte alignment is performed on re-
ceive. This configuration is appropriate for receiving a constant, uninterrupted stream of bit
data.
In the two examples shown in Figure D-23 and Figure D-24, if the CD (sync) pin is needed
as a parallel l/O line, clear the corresponding bit in the port A control PACNT) register. When
the bit is set, data will transmit using the CTS and receive using CD (sync), which, in this
case, is always internally asserted to the SCC.
MOTOROLA
CD (SYNC)
(OUTPUT)
(OUTPUT)
(INPUT)
(INPUT)
CD (SYNC)
RCLK
TCLK
RTS
CTS
(INPUT)
(INPUT)
(I/O)
(I/O)
TXD
RCLK
RXD
(I/O)
EXSYN = 1
NTSYN = 1
DIAG1-DIAG0 BITS = 11
L = 1 IN THE Tx BD
ONLY ONE Tx BD IS READY
DON'T
EXSYN = 1
NTSYN = 1
DIAG1-DIAG0 BITS = 11
CARE
Figure D-23. Simplest Transmit Case in NMSI
Figure D-24. Simplest Receive Case in NMSI
DATA BITS ARE SAMPLED AT EVERY RISING EDGE OF RCLK
FIRST BIT OF DATA IN BUFFER
NO BYTE ALIGNMENT PERFORMED ON RECEIVE
MC68302 USER’S MANUAL
LAST BIT OF DATA
MC68302 Applications
D-53