MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 351

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

APPENDIX D
MC68302 APPLICATIONS
This appendix describes different applications for the MC68302.
D.1 MINIMUM SYSTEM CONFIGURATION
The following paragraphs describe a minimum 16-bit MC68302 system. As Figure D-1
shows, this system can be easily built with very few components.
D.1.1 System Configuration
The crystal circuit shown in Figure D-1 is a typical configuration. The values used are not
required by Motorola. Some deviation of the capacitance or resistance values is allowed.
is
Crystal parameters need not be anything special—Co < 10 pF and Rx = 50
used. Of
course, an oscillator could be used in place of the crystal circuit.
AVEC is pulled high since autovectoring for external interrupts is not needed. If external de-
vices were added (not shown) the MC68302 interrupt controller could handle the interrupt
vector generation for up to seven external sources using IRQ7, IRQ6, 1RQ1, PB11, PB10,
PB9, and PB8. The IPL2-lPL0 lines are also pulled high (inactive) since no external inter-
rupts are required.
BUSW is pulled high for 16-bit operation and may not be modified dynamically. Choice of 8-
bit operation could be used to eliminate two of the memory chips.
BERR is pulled high since it is an open-drain signal. It will be asserted low by the MC68302
if the hardware watchdog terminates a stalled bus cycle.
BR is tied high since no external bus masters exist in this design.
BGACK is pulled high (inactive). It is asserted low during an IDMA or SDMA bus cycle.
FRZ is tied high since the MC68302 freeze debugging logic is not used in this design.
DISCPU is tied low to allow the M68000 core to function normally. Tying this pin high causes
the part to enter the disable CPU mode when the core is disabled and the part is an intelli-
gent peripheral.
All unused lines should be terminated.
MOTOROLA
MC68302 USER’S MANUAL
D-1